Instance Constructors
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new
ClientTileLinkIOArbiter(arbN: Int)
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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def
<>(src: Module): Unit
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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def
addClock(clock: Clock): Unit
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def
addDefaultReset: Unit
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def
addModule[T <: Module](c: ⇒ T)(implicit p: Parameters): T
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def
addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T
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def
addPin[T <: Data](pin: T, name: String): T
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def
addResetPin(reset: Bool): Bool
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val
amoAluOperandBits: Int
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def
apply(name: String): Data
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val
arbN: Int
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final
def
asInstanceOf[T0]: T0
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def
assert(cond: Bool, message: String): Unit
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val
asserts: ArrayBuffer[Assert]
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def
bfs(visit: (Node) ⇒ Unit): Unit
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val
bindings: ArrayBuffer[Binding]
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val
children: ArrayBuffer[Module]
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def
clientSourcedClientXactId(in: ClientSourcedWithId, id: Int): UInt
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var
clock: Clock
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val
clocks: ArrayBuffer[Clock]
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def
clone(): AnyRef
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def
debug(x: Node): Unit
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val
debugs: LinkedHashSet[Node]
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var
defaultResetPin: Bool
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var
defaultWidth: Int
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def
dfs(visit: (Node) ⇒ Unit): Unit
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def
emitDec(b: Backend): String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(that: Any): Boolean
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def
finalize(): Unit
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def
findBinding(m: Node): Option[Binding]
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final
def
getClass(): Class[_]
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def
getClassValNames(c: Class[_]): ArrayBuffer[String]
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def
getPathName(separator: String): String
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def
getPathName: String
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def
getValNames: ArrayBuffer[String]
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def
hasClock: Boolean
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var
hasExplicitClock: Boolean
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var
hasExplicitReset: Boolean
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def
hasReset: Boolean
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def
hasWhenCond: Boolean
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val
hashCode: Int
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def
hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]): Unit
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def
hookupFinish[M <: LogicalNetworkIO[Finish]](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]): Unit
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def
hookupManagerSourceBroadcast[M <: Data](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]): Unit
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def
hookupManagerSourceHeaderlessWithId[M <: ManagerSourcedWithId](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]): Unit
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val
io: Bundle { ... /* 2 definitions in type refinement */ }
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var
ioVal: Data
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def
isInput(node: Node): Boolean
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final
def
isInstanceOf[T0]: Boolean
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def
keepInputs(nodes: Seq[Node]): Seq[Node]
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var
level: Int
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def
managerSourcedClientXactId(in: ManagerSourcedWithId): UInt
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def
markComponent(): Unit
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var
moduleName: String
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var
name: String
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var
named: Boolean
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val
names: HashMap[String, Node]
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final
def
ne(arg0: AnyRef): Boolean
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def
nextIndex: Int
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var
nindex: Int
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val
nodes: LinkedHashSet[Node]
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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def
ownIo(): Unit
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lazy val
params: Parameters
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var
parent: Module
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var
pathParent: Module
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def
printf(message: String, args: Node*): Unit
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val
printfs: ArrayBuffer[Printf]
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def
removeInputs(nodes: Seq[Node]): Seq[Node]
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def
reset: Bool
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def
reset_=(): Unit
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def
reset_=(r: Bool): Unit
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val
resets: HashMap[Bool, Bool]
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def
stripComponent(s: String): String
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val
switchKeys: Stack[Bits]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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val
tlAcquireTypeBits: Int
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val
tlAcquireUnionBits: Int
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val
tlBeatAddrBits: Int
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val
tlBlockAddrBits: Int
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val
tlByteAddrBits: Int
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val
tlClientIdBits: Int
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val
tlClientXactIdBits: Int
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val
tlDataBeats: Int
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val
tlDataBits: Int
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val
tlDataBytes: Int
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val
tlGrantTypeBits: Int
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val
tlManagerIdBits: Int
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val
tlManagerXactIdBits: Int
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val
tlMaxClientXacts: Int
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val
tlMaxClientsPerPort: Int
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val
tlMaxManagerXacts: Int
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val
tlMemoryOpcodeBits: Int
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val
tlMemoryOperandSizeBits: Int
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val
tlNCachelessClients: Int
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val
tlNCachingClients: Int
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val
tlNClients: Int
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val
tlNManagers: Int
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val
tlNetworkDoesNotInterleaveBeats: Boolean
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val
tlNetworkPreservesPointToPointOrdering: Boolean
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val
tlWriteMaskBits: Int
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def
toString(): String
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var
traversal: Int
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var
verilog_parameters: String
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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def
whenCond: Bool
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val
whenConds: Stack[Bool]
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def
wires: Array[(String, Bits)]
Inherited from UsesParameters
Inherited from Module
Inherited from AnyRef
Inherited from Any
Concrete client-side arbiter that appends the arbiter's port id to client_xact_id