Instance Constructors
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new
L2MetaResp()
Value Members
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final
def
!=(arg0: AnyRef): Boolean
-
final
def
!=(arg0: Any): Boolean
-
def
##[T <: Data](right: T): L2MetaResp.this.type
-
def
##(b: Node): Node
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final
def
##(): Int
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def
+(other: Bundle): Bundle
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def
:=(that: Data): Unit
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def
<>(src: Node): Unit
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final
def
==(arg0: AnyRef): Boolean
-
final
def
==(arg0: Any): Boolean
-
def
===[T <: Data](right: T): Bool
-
def
W0Wtransform(): Unit
-
def
^^(src: Node): Unit
-
val
_id: Int
-
def
_isComplementOf(x: Node): Boolean
-
def
addConsumers(): Unit
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val
amoAluOperandBits: Int
-
def
apply(name: String): Data
-
def
asDirectionless(): L2MetaResp.this.type
-
def
asInput(): L2MetaResp.this.type
-
final
def
asInstanceOf[T0]: T0
-
def
asOutput(): L2MetaResp.this.type
-
def
assign(src: Node): Unit
-
val
blockAddrBits: Int
-
val
blockOffBits: Int
-
def
canCSE: Boolean
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lazy val
chiselName: String
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var
clock: Clock
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def
clone(): L2MetaResp.this.type
-
var
cntrIdx: Int
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val
code: Code
-
def
colonEquals(src: Bundle): Unit
-
def
colonEquals[T <: Data](that: Iterable[T]): Unit
-
def
colonEquals(that: Bits): Unit
-
var
comp: proc
-
var
component: Module
-
def
componentOf: Module
-
val
consumers: LinkedHashSet[Node]
-
def
contains(name: String): Boolean
-
def
dblLitValue: Double
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var
depth: Int
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var
driveRand: Boolean
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lazy val
elements: LinkedHashMap[String, Data]
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lazy val
emitIndex: Int
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final
def
eq(arg0: AnyRef): Boolean
-
def
equals(that: Any): Boolean
-
def
equalsForCSE(x: Node): Boolean
-
def
extract(b: Bundle): List[Node]
-
def
extract(widths: Array[Int]): List[UInt]
-
def
finalize(): Unit
-
def
flatten: Array[(String, Bits)]
-
def
flip(): L2MetaResp.this.type
-
def
floLitValue: Float
-
def
forceMatchingWidths: Unit
-
def
fromBits(b: Bits): L2MetaResp.this.type
-
def
fromMap(elemmap: Map[String, Data]): L2MetaResp.this.type
-
def
fromNode(n: Node): L2MetaResp.this.type
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final
def
getClass(): Class[_]
-
def
getLit: Literal
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def
getNode: Node
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def
getWidth(): Int
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def
getWidthW(): Width
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def
hashCode(): Int
-
def
hashCodeForCSE: Int
-
val
id: UInt
-
val
idxBits: Int
-
val
idxLSB: Int
-
val
idxMSB: Int
-
val
ignoresWriteMask: Boolean
-
def
illegalAssignment(that: Any): Unit
-
def
infer: Boolean
-
var
inferWidth: (⇒ Node) ⇒ Width
-
def
init(n: String, w: Int, ins: Node*): Node
-
def
init(n: String, widthFunc: (⇒ Node) ⇒ Width, ins: Node*): Node
-
def
initOf(n: String, widthfunc: (⇒ Node) ⇒ Width, ins: Iterable[Node]): Node
-
val
innerBeatAddrBits: Int
-
val
innerByteAddrBits: Int
-
val
innerDataBeats: Int
-
val
innerDataBits: Int
-
def
innerTLParams: Parameters
-
val
inputs: ArrayBuffer[Node]
-
val
internalDataBeats: Int
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def
isByValue: Boolean
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val
isDM: Boolean
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def
isDirectionless: Boolean
-
lazy val
isInObject: Boolean
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lazy val
isInVCD: Boolean
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final
def
isInstanceOf[T0]: Boolean
-
def
isIo: Boolean
-
def
isIo_=(isIo: Boolean): Unit
-
def
isKnownWidth: Boolean
-
val
isLastLevelCache: Boolean
-
final
def
isLit: Boolean
-
def
isReg: Boolean
-
def
isTopLevelIO: Boolean
-
var
isTypeNode: Boolean
-
def
isUsedByClockHi: Boolean
-
var
isWidthWalked: Boolean
-
val
line: StackTraceElement
-
def
litOf: Literal
-
def
litValue(default: BigInt): BigInt
-
def
matchWidth(w: Width): Node
-
def
maybeFlatten: Seq[Node]
-
-
var
modified: Boolean
-
val
nAcquireTransactors: Int
-
val
nReleaseTransactors: Int
-
val
nSecondaryMisses: Int
-
val
nSets: Int
-
val
nTransactors: Int
-
val
nWays: Int
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var
name: String
-
var
nameHolder: nameable
-
def
nameIt(path: String, isNamingIo: Boolean): Unit
-
var
named: Boolean
-
final
def
ne(arg0: AnyRef): Boolean
-
def
needWidth(): Int
-
final
def
notify(): Unit
-
final
def
notifyAll(): Unit
-
val
outerBeatAddrBits: Int
-
val
outerByteAddrBits: Int
-
val
outerDataBeats: Int
-
val
outerDataBits: Int
-
def
outerTLParams: Parameters
-
def
params: Parameters
-
var
parents: LinkedHashSet[Node]
-
def
printTree(writer: PrintStream, depth: Int, indent: String): Unit
-
var
prune: Boolean
-
val
refillCycles: Int
-
val
refillCyclesPerBeat: Int
-
def
removeTypeNodes(): Unit
-
def
replaceTree(newNode: Node): Unit
-
def
review(): Unit
-
val
rowBits: Int
-
val
rowBytes: Int
-
val
rowOffBits: Int
-
var
sccIndex: Int
-
var
sccLowlink: Int
-
def
setIsTypeNode: Unit
-
def
setName(n: String): Unit
-
def
setWidth(w: Int): Unit
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
-
val
tagBits: Int
-
val
tag_match: Bool
-
def
toBits(): UInt
-
def
toBool(): Bool
-
lazy val
toNode: Node
-
def
toString(): String
-
val
untagBits: Int
-
def
usesInClockHi(i: Node): Boolean
-
val
view: Seq[String]
-
final
def
wait(): Unit
-
final
def
wait(arg0: Long, arg1: Int): Unit
-
final
def
wait(arg0: Long): Unit
-
val
wayBits: Int
-
val
way_en: UInt
-
var
width_: Width
Inherited from UsesParameters
Inherited from Bundle
Inherited from Aggregate
Inherited from Data
Inherited from Node
Inherited from nameable
Inherited from AnyRef
Inherited from Any
