Instance Constructors
-
new
Release()
Value Members
-
final
def
!=(arg0: AnyRef): Boolean
-
final
def
!=(arg0: Any): Boolean
-
def
##[T <: Data](right: T): Release.this.type
-
def
##(b: Node): Node
-
final
def
##(): Int
-
def
+(other: Bundle): Bundle
-
def
:=(that: Data): Unit
-
def
<>(src: Node): Unit
-
final
def
==(arg0: AnyRef): Boolean
-
final
def
==(arg0: Any): Boolean
-
def
===[T <: Data](right: T): Bool
-
def
W0Wtransform(): Unit
-
def
^^(src: Node): Unit
-
val
_id: Int
-
def
_isComplementOf(x: Node): Boolean
-
def
addConsumers(): Unit
-
val
addr_beat: UInt
-
val
addr_block: UInt
-
val
amoAluOperandBits: Int
-
def
apply(name: String): Data
-
def
asDirectionless(): Release.this.type
-
def
asInput(): Release.this.type
-
final
def
asInstanceOf[T0]: T0
-
def
asOutput(): Release.this.type
-
def
assign(src: Node): Unit
-
def
canCSE: Boolean
-
lazy val
chiselName: String
-
val
client_xact_id: UInt
-
var
clock: Clock
-
def
clone(): Release.this.type
-
var
cntrIdx: Int
-
def
colonEquals(src: Bundle): Unit
-
def
colonEquals[T <: Data](that: Iterable[T]): Unit
-
def
colonEquals(that: Bits): Unit
-
var
comp: proc
-
var
component: Module
-
def
componentOf: Module
-
def
conflicts(addr: UInt): Bool
-
-
val
consumers: LinkedHashSet[Node]
-
def
contains(name: String): Boolean
-
val
data: UInt
-
def
dblLitValue: Double
-
var
depth: Int
-
var
driveRand: Boolean
-
lazy val
elements: LinkedHashMap[String, Data]
-
lazy val
emitIndex: Int
-
final
def
eq(arg0: AnyRef): Boolean
-
def
equals(that: Any): Boolean
-
def
equalsForCSE(x: Node): Boolean
-
def
extract(b: Bundle): List[Node]
-
def
extract(widths: Array[Int]): List[UInt]
-
def
finalize(): Unit
-
def
flatten: Array[(String, Bits)]
-
def
flip(): Release.this.type
-
def
floLitValue: Float
-
def
forceMatchingWidths: Unit
-
def
fromBits(b: Bits): Release.this.type
-
def
fromMap(elemmap: Map[String, Data]): Release.this.type
-
def
fromNode(n: Node): Release.this.type
-
final
def
getClass(): Class[_]
-
def
getLit: Literal
-
def
getNode: Node
-
def
getWidth(): Int
-
def
getWidthW(): Width
-
def
hasData(dummy: Int = 0): Bool
-
def
hasMultibeatData(dummy: Int = 0): Bool
-
def
hashCode(): Int
-
def
hashCodeForCSE: Int
-
def
illegalAssignment(that: Any): Unit
-
def
infer: Boolean
-
var
inferWidth: (⇒ Node) ⇒ Width
-
def
init(n: String, w: Int, ins: Node*): Node
-
def
init(n: String, widthFunc: (⇒ Node) ⇒ Width, ins: Node*): Node
-
def
initOf(n: String, widthfunc: (⇒ Node) ⇒ Width, ins: Iterable[Node]): Node
-
val
inputs: ArrayBuffer[Node]
-
def
is(t: UInt): Bool
-
def
isByValue: Boolean
-
def
isDirectionless: Boolean
-
lazy val
isInObject: Boolean
-
lazy val
isInVCD: Boolean
-
final
def
isInstanceOf[T0]: Boolean
-
def
isIo: Boolean
-
def
isIo_=(isIo: Boolean): Unit
-
def
isKnownWidth: Boolean
-
final
def
isLit: Boolean
-
def
isReg: Boolean
-
def
isTopLevelIO: Boolean
-
var
isTypeNode: Boolean
-
def
isUsedByClockHi: Boolean
-
def
isVoluntary(dummy: Int = 0): Bool
-
var
isWidthWalked: Boolean
-
val
line: StackTraceElement
-
def
litOf: Literal
-
def
litValue(default: BigInt): BigInt
-
def
matchWidth(w: Width): Node
-
def
maybeFlatten: Seq[Node]
-
var
modified: Boolean
-
var
name: String
-
var
nameHolder: nameable
-
def
nameIt(path: String, isNamingIo: Boolean): Unit
-
var
named: Boolean
-
final
def
ne(arg0: AnyRef): Boolean
-
def
needWidth(): Int
-
final
def
notify(): Unit
-
final
def
notifyAll(): Unit
-
def
params: Parameters
-
var
parents: LinkedHashSet[Node]
-
def
printTree(writer: PrintStream, depth: Int, indent: String): Unit
-
var
prune: Boolean
-
val
r_type: UInt
-
def
removeTypeNodes(): Unit
-
def
replaceTree(newNode: Node): Unit
-
def
requiresAck(dummy: Int = 0): Bool
-
def
review(): Unit
-
var
sccIndex: Int
-
var
sccLowlink: Int
-
def
setIsTypeNode: Unit
-
def
setName(n: String): Unit
-
def
setWidth(w: Int): Unit
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
-
val
tlAcquireTypeBits: Int
-
val
tlAcquireUnionBits: Int
-
val
tlBeatAddrBits: Int
-
val
tlBlockAddrBits: Int
-
val
tlByteAddrBits: Int
-
val
tlClientIdBits: Int
-
val
tlClientXactIdBits: Int
-
-
val
tlDataBeats: Int
-
val
tlDataBits: Int
-
val
tlDataBytes: Int
-
val
tlGrantTypeBits: Int
-
val
tlManagerIdBits: Int
-
val
tlManagerXactIdBits: Int
-
val
tlMaxClientXacts: Int
-
val
tlMaxClientsPerPort: Int
-
val
tlMaxManagerXacts: Int
-
val
tlMemoryOpcodeBits: Int
-
val
tlMemoryOperandSizeBits: Int
-
val
tlNCachelessClients: Int
-
val
tlNCachingClients: Int
-
val
tlNClients: Int
-
val
tlNManagers: Int
-
val
tlNetworkDoesNotInterleaveBeats: Boolean
-
val
tlNetworkPreservesPointToPointOrdering: Boolean
-
val
tlWriteMaskBits: Int
-
def
toBits(): UInt
-
def
toBool(): Bool
-
lazy val
toNode: Node
-
def
toString(): String
-
def
usesInClockHi(i: Node): Boolean
-
val
view: Seq[String]
-
val
voluntary: Bool
-
final
def
wait(): Unit
-
final
def
wait(arg0: Long, arg1: Int): Unit
-
final
def
wait(arg0: Long): Unit
-
var
width_: Width
Inherited from UsesParameters
Inherited from Bundle
Inherited from Aggregate
Inherited from Data
Inherited from Node
Inherited from nameable
Inherited from AnyRef
Inherited from Any
The Release channel is used to release data or permission back to the manager in response to uncore.Probe messages. It can also be used to voluntarily write back data, for example in the event that dirty data must be evicted on a cache miss. The available types of Release messages are always customized by a particular uncore.CoherencePolicy. Releases may contain data or may be simple acknowledgements. Voluntary Releases are acknowledged with Grants.