44#define SET_BITS(REG, BIT) ((REG) |= (BIT))
45#define CLEAR_BITS(REG, BIT) ((REG) &= ~(BIT))
46#define READ_BITS(REG, BIT) ((REG) & (BIT))
47#define WRITE_BITS(REG, CLEARMASK, SETMASK) ((REG) = (((REG) & (~(CLEARMASK))) | (SETMASK)))
51#define READ_CSR(REG) ({ \
52 unsigned long __tmp; \
53 asm volatile ("csrr %0, " REG : "=r"(__tmp)); \
56#define WRITE_CSR(REG, VAL) ({ \
57 asm volatile ("csrw " REG ", %0" :: "rK"(VAL)); })
59#define SWAP_CSR(REG, VAL) ({ \
60 unsigned long __tmp; \
61 asm volatile ("csrrw %0, " REG ", %1" : "=r"(__tmp) : "rK"(VAL)); \
64#define SET_CSR_BITS(REG, BIT) ({ \
65 unsigned long __tmp; \
66 asm volatile ("csrrs %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
69#define CLEAR_CSR_BITS(REG, BIT) ({ \
70 unsigned long __tmp; \
71 asm volatile ("csrrc %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
@ HIGH
Definition: rv.h:84
@ RESET
Definition: rv.h:77
@ ENABLE
Definition: rv.h:81
@ DISABLE
Definition: rv.h:80
Status
Definition: rv.h:87
@ ERROR
Definition: rv.h:89
@ BUSY
Definition: rv.h:90
@ TIMEOUT
Definition: rv.h:91