Instance Constructors
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new
L2WritebackUnit(trackerId: Int)
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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def
<>(src: Module): Unit
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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def
addClock(clock: Clock): Unit
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def
addDefaultReset: Unit
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def
addModule[T <: Module](c: ⇒ T)(implicit p: Parameters): T
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def
addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T
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def
addPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]): UInt
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def
addPendingBitInternal[T <: HasL2BeatAddr](in: DecoupledIO[T]): UInt
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def
addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt
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def
addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt
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def
addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt
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def
addPendingBitWhenBeatIsGetOrAtomic(in: DecoupledIO[AcquireFromSrc]): UInt
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def
addPin[T <: Data](pin: T, name: String): T
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def
addResetPin(reset: Bool): Bool
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val
amoAluOperandBits: Int
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def
apply(name: String): Data
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final
def
asInstanceOf[T0]: T0
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def
assert(cond: Bool, message: String): Unit
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val
asserts: ArrayBuffer[Assert]
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def
bfs(visit: (Node) ⇒ Unit): Unit
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val
bindings: ArrayBuffer[Binding]
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val
blockAddrBits: Int
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val
blockOffBits: Int
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val
children: ArrayBuffer[Module]
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var
clock: Clock
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val
clocks: ArrayBuffer[Clock]
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def
clone(): AnyRef
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val
code: Code
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def
connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool): (UInt, Bool)
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def
connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt): (UInt, Bool)
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def
connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool
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def
connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool
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def
connectInternalDataBeatCounter[T <: HasL2Data](in: ValidIO[T], full_block: Bool = Bool(true)): Bool
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def
connectInternalDataBeatCounter[T <: HasL2BeatAddr](in: DecoupledIO[T], beat: UInt = UInt(0), full_block: Bool = Bool(true)): (UInt, Bool)
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def
connectOutgoingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T], beat: UInt = UInt(0)): (UInt, Bool)
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def
connectTwoWayBeatCounter[T <: TileLinkChannel, S <: TileLinkChannel](max: Int, up: DecoupledIO[T], down: DecoupledIO[S], beat: UInt = UInt(0), track: (T) ⇒ Bool = (t: T) => Bool(true)): (Bool, UInt, Bool, UInt, Bool)
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val
curr_probe_dst: UInt
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val
curr_read_beat: UInt
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val
data_buffer: Vec[UInt]
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def
debug(x: Node): Unit
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val
debugs: LinkedHashSet[Node]
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var
defaultResetPin: Bool
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var
defaultWidth: Int
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def
dfs(visit: (Node) ⇒ Unit): Unit
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def
dropPendingBit[T <: HasL2BeatAddr](in: DecoupledIO[T]): UInt
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def
dropPendingBitAtDest(in: DecoupledIO[ProbeToDst]): UInt
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def
dropPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]): UInt
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def
dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt
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def
dropPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt
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def
emitDec(b: Backend): String
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(that: Any): Boolean
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def
finalize(): Unit
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def
findBinding(m: Node): Option[Binding]
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final
def
getClass(): Class[_]
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def
getClassValNames(c: Class[_]): ArrayBuffer[String]
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def
getPathName(separator: String): String
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def
getPathName: String
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def
getValNames: ArrayBuffer[String]
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def
hasClock: Boolean
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var
hasExplicitClock: Boolean
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var
hasExplicitReset: Boolean
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def
hasReset: Boolean
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def
hasWhenCond: Boolean
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val
hashCode: Int
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val
idxBits: Int
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val
idxLSB: Int
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val
idxMSB: Int
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val
ignoresWriteMask: Boolean
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val
innerBeatAddrBits: Int
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val
innerByteAddrBits: Int
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val
innerDataBeats: Int
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val
innerDataBits: Int
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def
innerTLParams: Parameters
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val
internalDataBeats: Int
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var
ioVal: Data
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val
isDM: Boolean
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def
isInput(node: Node): Boolean
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final
def
isInstanceOf[T0]: Boolean
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val
isLastLevelCache: Boolean
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def
keepInputs(nodes: Seq[Node]): Seq[Node]
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var
level: Int
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def
markComponent(): Unit
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var
moduleName: String
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val
nAcquireTransactors: Int
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val
nReleaseTransactors: Int
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val
nSecondaryMisses: Int
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val
nSets: Int
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val
nTransactors: Int
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val
nWays: Int
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var
name: String
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var
named: Boolean
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val
names: HashMap[String, Node]
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final
def
ne(arg0: AnyRef): Boolean
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def
nextIndex: Int
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var
nindex: Int
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val
nodes: LinkedHashSet[Node]
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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val
ognt_data_done: Bool
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val
ognt_data_idx: UInt
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val
orel_data_done: Bool
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val
orel_data_idx: UInt
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val
outerBeatAddrBits: Int
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val
outerByteAddrBits: Int
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val
outerDataBeats: Int
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val
outerDataBits: Int
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def
outerTLParams: Parameters
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def
ownIo(): Unit
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lazy val
params: Parameters
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var
parent: Module
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var
pathParent: Module
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val
pending_iprbs: UInt
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val
pending_irels: Bool
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val
pending_ognt: Bool
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val
pending_orel_data: UInt
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val
pending_reads: UInt
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val
pending_resps: UInt
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def
pinAllReadyValidLow[T <: Data](b: Bundle): Unit
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def
printf(message: String, args: Node*): Unit
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val
printfs: ArrayBuffer[Printf]
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val
refillCycles: Int
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val
refillCyclesPerBeat: Int
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def
removeInputs(nodes: Seq[Node]): Seq[Node]
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def
reset: Bool
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def
reset_=(): Unit
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def
reset_=(r: Bool): Unit
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val
resets: HashMap[Bool, Bool]
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val
rowBits: Int
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val
rowBytes: Int
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val
rowOffBits: Int
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val
s_busy: UInt
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val
s_idle: UInt
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val
s_inner_probe: UInt
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val
s_outer_grant: UInt
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val
s_wb_resp: UInt
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val
state: UInt
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def
stripComponent(s: String): String
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val
switchKeys: Stack[Bits]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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val
tagBits: Int
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def
toString(): String
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var
traversal: Int
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val
untagBits: Int
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var
verilog_parameters: String
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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val
wayBits: Int
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def
whenCond: Bool
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val
whenConds: Stack[Bool]
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def
wires: Array[(String, Bits)]
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val
xact_addr_block: UInt
Inherited from UsesParameters
Inherited from Module
Inherited from AnyRef
Inherited from Any
