L2XactTracker

abstract def io: Data

final def !=(arg0: AnyRef): Boolean

final def !=(arg0: Any): Boolean

final def ##(): Int

def <>(src: Module): Unit

final def ==(arg0: AnyRef): Boolean

final def ==(arg0: Any): Boolean

def addClock(clock: Clock): Unit

def addDefaultReset: Unit

def addModule[T <: Module](c: ⇒ T)(implicit p: Parameters): T

def addModule[T <: Module](c: ⇒ T, f: PartialFunction[Any, Any]): T

def addPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]): UInt

def addPendingBitInternal[T <: HasL2BeatAddr](in: DecoupledIO[T]): UInt

def addPendingBitWhenBeat[T <: HasBeat](inc: Bool, in: T): UInt

def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt

def addPendingBitWhenBeatHasPartialWritemask(in: DecoupledIO[AcquireFromSrc]): UInt

def addPendingBitWhenBeatIsGetOrAtomic(in: DecoupledIO[AcquireFromSrc]): UInt

def addPin[T <: Data](pin: T, name: String): T

def addResetPin(reset: Bool): Bool

val amoAluOperandBits: Int

def apply(name: String): Data

final def asInstanceOf[T0]: T0

def assert(cond: Bool, message: String): Unit

val asserts: ArrayBuffer[Assert]

def bfs(visit: (Node) ⇒ Unit): Unit

val bindings: ArrayBuffer[Binding]

val blockAddrBits: Int

val blockOffBits: Int

val children: ArrayBuffer[Module]

var clock: Clock

val clocks: ArrayBuffer[Clock]

def clone(): AnyRef

val code: Code

def connectDataBeatCounter[S <: L2HellaCacheBundle](inc: Bool, data: S, beat: UInt, full_block: Bool): (UInt, Bool)

def connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt): (UInt, Bool)

Returns the current count on this channel and when a message is done

def connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool

Returns done but not cnt.

def connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool

Counter for beats on incoming DecoupledIO[LogicalNetworkIO[]]s returns done

def connectIncomingDataBeatCountersWithHeader[T <: TileLinkChannel with HasClientTransactionId](in: DecoupledIO[LogicalNetworkIO[T]], entries: Int, getId: (LogicalNetworkIO[T]) ⇒ UInt): Vec[Bool]

If the network might interleave beats from different messages, we need a Vec of counters, one for every outstanding message id that might be interleaved.

def connectInternalDataBeatCounter[T <: HasL2Data](in: ValidIO[T], full_block: Bool = Bool(true)): Bool

def connectInternalDataBeatCounter[T <: HasL2BeatAddr](in: DecoupledIO[T], beat: UInt = UInt(0), full_block: Bool = Bool(true)): (UInt, Bool)

def connectOutgoingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T], beat: UInt = UInt(0)): (UInt, Bool)

Counter for beats on outgoing chisel.DecoupledIO

def connectTwoWayBeatCounter[T <: TileLinkChannel, S <: TileLinkChannel](max: Int, up: DecoupledIO[T], down: DecoupledIO[S], beat: UInt = UInt(0), track: (T) ⇒ Bool = (t: T) => Bool(true)): (Bool, UInt, Bool, UInt, Bool)

Provides counters on two channels, as well a meta-counter that tracks how many messages have been sent over the up channel but not yet responded to over the down channel

def debug(x: Node): Unit

val debugs: LinkedHashSet[Node]

var defaultResetPin: Bool

var defaultWidth: Int

def dfs(visit: (Node) ⇒ Unit): Unit

def dropPendingBit[T <: HasL2BeatAddr](in: DecoupledIO[T]): UInt

def dropPendingBitAtDest(in: DecoupledIO[ProbeToDst]): UInt

def dropPendingBitInternal[T <: HasL2BeatAddr](in: ValidIO[T]): UInt

def dropPendingBitWhenBeat[T <: HasBeat](dec: Bool, in: T): UInt

def dropPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt

def emitDec(b: Backend): String

final def eq(arg0: AnyRef): Boolean

def equals(that: Any): Boolean

def finalize(): Unit

def findBinding(m: Node): Option[Binding]

final def getClass(): Class[_]

def getClassValNames(c: Class[_]): ArrayBuffer[String]

def getPathName(separator: String): String

def getPathName: String

def getValNames: ArrayBuffer[String]

def hasClock: Boolean

var hasExplicitClock: Boolean

var hasExplicitReset: Boolean

def hasReset: Boolean

def hasWhenCond: Boolean

val hashCode: Int

val idxBits: Int

val idxLSB: Int

val idxMSB: Int

val ignoresWriteMask: Boolean

val innerBeatAddrBits: Int

val innerByteAddrBits: Int

val innerDataBeats: Int

val innerDataBits: Int

def innerTLParams: Parameters

val internalDataBeats: Int

var ioVal: Data

val isDM: Boolean

def isInput(node: Node): Boolean

final def isInstanceOf[T0]: Boolean

val isLastLevelCache: Boolean

def keepInputs(nodes: Seq[Node]): Seq[Node]

var level: Int

def markComponent(): Unit

var moduleName: String

val nAcquireTransactors: Int

val nReleaseTransactors: Int

val nSecondaryMisses: Int

val nSets: Int

val nTransactors: Int

val nWays: Int

var name: String

var named: Boolean

val names: HashMap[String, Node]

final def ne(arg0: AnyRef): Boolean

def nextIndex: Int

var nindex: Int

val nodes: LinkedHashSet[Node]

final def notify(): Unit

final def notifyAll(): Unit

val outerBeatAddrBits: Int

val outerByteAddrBits: Int

val outerDataBeats: Int

val outerDataBits: Int

def outerTLParams: Parameters

def ownIo(): Unit

lazy val params: Parameters

var parent: Module

var pathParent: Module

def pinAllReadyValidLow[T <: Data](b: Bundle): Unit

def printf(message: String, args: Node*): Unit

val printfs: ArrayBuffer[Printf]

val refillCycles: Int

val refillCyclesPerBeat: Int

def removeInputs(nodes: Seq[Node]): Seq[Node]

def reset: Bool

def reset_=(): Unit

def reset_=(r: Bool): Unit

val resets: HashMap[Bool, Bool]

val rowBits: Int

val rowBytes: Int

val rowOffBits: Int

def stripComponent(s: String): String

val switchKeys: Stack[Bits]

final def synchronized[T0](arg0: ⇒ T0): T0

val tagBits: Int

def toString(): String

var traversal: Int

val untagBits: Int

var verilog_parameters: String

final def wait(): Unit

final def wait(arg0: Long, arg1: Int): Unit

final def wait(arg0: Long): Unit

val wayBits: Int

def whenCond: Bool

val whenConds: Stack[Bool]

def wires: Array[(String, Bits)]