riscv.h

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#ifndef __RISCV_H
#define __RISCV_H
 
#ifdef __riscv_xlen
  #define RISCV_XLEN __riscv_xlen
#else
  #warning "__riscv_xlen not defined, defaulting to 64"
  #define RISCV_XLEN 64
#endif
 
#if RISCV_XLEN == 64
  #define LREG ld
  #define SREG sd
  #define REGBYTES 8
#elif RISCV_XLEN == 32
  #define LREG lw
  #define SREG sw
  #define REGBYTES 4
#else
  #error "Unsupported RISCV_XLEN"
#endif
 
 
/* ================ RISC-V specific definitions ================ */
#define READ_CSR(REG) ({                          \
  unsigned long __tmp;                            \
  asm volatile ("csrr %0, " REG : "=r"(__tmp));  \
  __tmp; })
 
#define WRITE_CSR(REG, VAL) ({                    \
  asm volatile ("csrw " REG ", %0" :: "rK"(VAL)); })
 
#define SWAP_CSR(REG, VAL) ({                     \
  unsigned long __tmp;                            \
  asm volatile ("csrrw %0, " REG ", %1" : "=r"(__tmp) : "rK"(VAL)); \
  __tmp; })
 
#define SET_CSR_BITS(REG, BIT) ({                 \
  unsigned long __tmp;                            \
  asm volatile ("csrrs %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
  __tmp; })
 
#define CLEAR_CSR_BITS(REG, BIT) ({               \
  unsigned long __tmp;                            \
  asm volatile ("csrrc %0, " REG ", %1" : "=r"(__tmp) : "rK"(BIT)); \
  __tmp; })
 
 
#endif /* __RISCV_H */